Data cache block release requests in a cache hierarchy with multiple levels

In response to executing a release command, a release request that specifies a target address of a target cache line, sent from a processor core to a cache memory of a lower level. In response, it is determined whether the target address hits in the cache memory of the lower level. In this case, the target cache line is maintained in a data array of the cache memory of the child level, and it is updated as a replacement order field of the cache memory of the lower level that the target cache line is more likely in response to a subsequent cache miss in a congruence class is cleaned up, which includes the target cache line. In response to the subsequent cache miss the target cache line is written by a castout operation in the cache memory of the lower level with an indication that the target cache line was a target of a previous release request of the processor core.