In Situ Silicon-Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction Using Multi-Impedance Method for Transistor Characterization

In this paper, the design and use of an in situ tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer tuner is limited by the frequency range and has high losses between this external tuner and the device under test (DUT). Here, the IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the tuner is based on variable lumped R and C elements fulfilled with cold-field-effect transistor and varactors controlled through biasing and associated to coplanar transmission line for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the four noise ( NF min , R n , Γ opt ) parameters of 65-nm metal-oxide-semiconductor field-effect silicon transistors through the use of this in situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing transistor capabilities at MMW.