Low-Frequency Noise Analysis Of On-Membrane Mosfet And In-Situ Thermal Annealing

In this work, we discuss the I-V and low-frequency noise characteristics of on-membrane 6$\mu$m-wide 1$\mu$m-long n-MOSFETs for analog low-power sensor interfaces, in e.g. pressure or gas measurements. After MEMS processing (i.e. bulk Si Deep Reactive Ion Etching), a high power spectral density (PSD) with clear signs of Random Telegraph Noise (RTN) (with $\Delta$Id/Id as high as 40%) is observed. Cadence simulations predict lower PSD values. At the same time, the MOSFET I-V measurements show threshold voltage, transconductance and subthreshold slope discrepancies compared to simulations. In order to heal these detrimental effects of DRIE, a high-temperature in-situ thermal annealing ($T=265^{\circ}$C for 2 min) is applied. As a result, the noise power is reduced by a factor of about 10, the MOSFET electrical characteristics are also partially recovered and become close to simulations. An analytical study based on noise and current models fits the interpretation of effects linked to interface traps.