A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.