Enhancing the Performance of FPGA Congestion Management via Supervised Learning

Placement remains one of the most critical steps in the FPGA design flow. In this paper, a novel machine learning framework that enables a placement tool to predict key parameters used to inflate Look-Up-Tables (LUTS) during placement is proposed. LUT inflation assists the placer in spreading cells in congested regions to reduce congestion and improve routability. Empirical results show that when employed in a state-of-the-art placement tool, the proposed framework improves routed wirelength and increases the total number of routable placements found.