Panel Level Warpage Simulation of Printed Circuit Boards comprising electrical components

Regarding printed circuit board industry, panel level warpage is a fundamental issue leading to problems regarding both producibility of the printed circuit boards at manufacturer side and reliability of the final products at customer side. Embedded component technology is particularly affected by warpage issues due to asymmetric stack-ups and the mismatch in mechanical and thermal material properties of the board materials and the embedded silicon dies. Consequently, finite element simulations of printed circuit board warpage on panel level are becoming increasingly important; identifying unsuitable board designs and stack-ups prior to manufacturing prevents warpage related problems in the first place and thus efficiently saves resources as well as production time and costs. The current study deals with finite element simulations of printed circuit boards comprising electrical components to identify the remaining board warpage after cooling down from lamination temperature.Understanding the main factors influencing the warpage behavior and how to take them into account by simulation is crucial for achieving reliable simulation results. Next to the mismatch in the coefficient of thermal expansion of the different materials, cure-induced resin shrinkage turned out to be a main driver of printed circuit board warpage. Our main focus is therefore on material testing and the correct implementation of the measured material properties into the finite element software Abaqus/CAE. A measurement method was developed which allows to measure the cure shrinkage of pure resin samples using thermo-mechanical analysis. The measured shrinkage was implemented into the material model of the resin and is thus considered in simulation, as well as temperature-dependent thermal and mechanical properties of all materials and the orthotropic behavior of the fiber-reinforced composites.A 3-D model of a printed circuit board was created in Abaqus/CAE using conventional shell elements. The stack-up was implemented as a composite layup, considering all copper and FR4 layers, the electrical dies and the pure resin enclosing the dies. A predefined temperature field represents the actual temperature conditions in the press, starting at lamination temperature and cooling down to room temperature after curing. During the first step at high temperatures, cure shrinkage is applied to the resin, representing the curing of the resin-based constituents of the board in the press; applying the resin shrinkage already leads to a first deviation from the initial flat and stress-free condition. Driven by the differences in the coefficient of thermal expansion of all the materials, the deformation increases during the second step while cooling, until at room temperature the final warped state is reached. The maximum deformation at the corners of the model was then evaluated with regard to the initial flat state.Comparison of the simulation results and the measurement values of warped boards shows very good agreement. The overall panel warpage as well as the deformation of the individual arrays positioned on the panel could be predicted with sufficient accuracy. Variations in the stack-up of the board in order to reduce warpage were modeled as well, the simulation results showing the same trend in warpage behavior as the boards actually produced. Based on these results it could be shown that the presented simulation approach is suitable for describing warpage of printed circuit boards on panel level.