Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \vert {V_{t}}\vert +{2\,V_{ds,sat}} and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 μm N-well process with a 3 V supply are given.