A faster approach to add Multi operands using unified pipelining technique

Abstract The article presents novel multi operand adder using seamless pipelining concept. The proposed adder synthesized using Xilinx 14.2 software and implemented on Virtex-5(xc5vfx30t-3ff665) device. Delay and device utilization parameter i.e. number of slice LUTs are compared with carry propagate adder (CPA), carry save adder (CSA), and conventional pipelined adder. And it shows our method gives the highest frequency of operation among all the methods.