Developing 3D Heterogeneous Structures for Future Chips

This paper reviews recent advances in developing 3D heterogeneous integration technologies and heterogeneous structures in CMOS for smart chips. The demonstrated 3D CMOS-compatible 3D heterogeneous structures include transistor-size stacked-via type vertical magnetic-cored inductors, above-IC nano crossbar array and graphene-based NEMS switch ESD protection structures, and through-backend-of-line (BEOL) metal wall structures for global fly-noise isolation. These novel 3D heterogeneous structures were validated experimentally and are potential enablers for smart future chips in CMOS.