A Low-Power and Cost-Effective AES Chip Design for Healthcare Devices

Abstract—Information security is very important to health information, and Cryptography is the key measure for information security. This paper proposes a low-power and cost-effective implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. Considering the low-power, we present a mixed pipelining architecture. The performance is evaluated on SMIC 0.18um CMOS technology and the throughput achieves at 800Mbps with the cost of only 17519 equivalent NAND2 gates, and the power consumption is only 9.7mw. Keywords-resource-sharing, mixed pipelining, AES