Method and apparatus for the high speed dram establish a desired read latency maintained

Provided is a memory device, to compensate for variations in the delay amount for the data flow of the read clock, to provide a method and apparatus for maintaining a specified read latency. The A delay amount of uncertainty and variability with respect to data flow of the read clock to compensate to achieve the specified read latency, and method for managing variable timing of the internal clock signal derived from the external clock signal to provide a device. Raster signals generated in the initialization of the DRAM, to start the first counter for counting the number of cycles the external clock, the second counter through the slave delay line of the delay locked loops to start. These counters continuously operated to start once the difference between these count values ​​represent the internal delay in cycles external clock signal. By offsetting one of the counters with the internal read latency represents the internal read latency of DRAM circuits. Once the counter which is not offset is equal to the counter that is offset, the read data out to the output line at specified read latency, synchronized to an external read clock.