Manufacturability-aware mask assignment in multiple patterning lithography

Due to the progress of the process technology, multiple patterning lithography (MPL) is one of the most promising techniques in the 22 nm logic node and beyond. In MPL, features are iteratively formed onto a wafer by exposures. Mask misalignment is caused during MPL process and it reduces the yield of the produced LSI in MPL. To prevent yield loss caused by the mask misalignment, mask assignment methods that take the manufacturability into consideration are desired. Recent mask assignment techniques in MPL are introduced.