Latchup test failure from ESD protection circuit activation beyond ESD stress condition

Latchup test failures occurred at two IO pins of an IC. Failure analysis revealed damage at the ESD device of a neighboring power pin's ESD protection circuit. To identify the root cause of the problem, the behavior of the ESD circuit in response to the latchup trigger signal was monitored. The ESD protection circuit was found to anomalously respond to even DC-like latchup trigger pulses. A layout and circuit study identified a possible rare failure mode and subsequent experiments validated the suspected failure mechanism. A simple circuit modification successfully solved the issue without affecting discharge characteristic and ESD performance of the IC. (Abstract)