Clock controlled Hybrid-latch flip-flops design

In order to obtain power efficient flip-flops, two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse generator. HSPCE simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced design. They can reduce 44.5% and 51.4% power dissipation, 29.2%and 44.5% clock-to-output latency and 65.6% and 68.4% PDP.