Improving yield learning by electrical fault inspection

Wafer sort is used to screen die before shipment. In addition, sort analysis on failing die provides fault localization leading to root cause and thus contributes to yield learning. However, there are cases where sort test cannot be completed, and as a result yield learning requires lengthy analyses on these die. Such cases are increasing as process geometries continue to shrink. This paper describes an image-based approach to the localization of electrical faults with a high physical failure analysis (PFA) success rate (>90%). Additionally, this approach is well-suited for foundry adoption and standardization as it does not require logic schematics.