Integrated self-test for stack architecture

An integrated self-test for a stack architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (Dynamic Random Access Memory) elements; and a system control element for the memory stack. The system element includes a built-in self test (BIST) engine in order to generate a Schreibprufereignis or a read test event for the memory stack, a test interface for receiving test data for the Schreibprufereignis or Leseprufereignisse of the BIST engine, and a memory controller wherein the memory controller receives a portion of the test data from the test interface and implements the at least Schreibprufereignis or read test event in the DRAM elements of the memory stack.