Reliability-Guided Design Space Exploration for Safety-Critical Applications

Technological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets(SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while responding to applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80% of systems on chips. To tackle this problem we propose a new memory reliability enhancement techniques called DPSR: Double Parity Single Redundancy, designed to answer SBU and MBU problematic. To evaluate our proposition we modify historically used simulation single fault injection model by adding memory monitoring and MBU injection and compare it to state of the art fault injection engines. Based on a thorough fault injection experiments, DPSR shows promising results. It detects and corrects more than 99.6% of encountered MBU and has a performance overhead of less than 3% in mean. Our fault injection methodology shows also promising results by discovering more than 11% of incorrect behavior after fault injection than the classical single bit random injection.