Effects of process and geometry scaling on SEU hardness

The dependence of SEU hardness on the scale of circuit integration in memories has been investigated experimentally and theoretically. Numerical simulations are used to separate effects of doping levels and vertical dimensions, which generally harden the cell with increasing integration, from effects of lateral dimension shrinkage, that have the opposite effect. These calculations are compared to SEU data from memories that were either (1) fabricated at Sandia using the CMOS-III 2..mu.. process or (2) fabricated at AT and T using identical lateral dimensions, but with processes characteristic of the AT and T 1..mu.. technology, i.e., different vertical dimensions and doping levels.