Multilayer Buffer System for Fabrication of High-T(sub c) Edge-Geometry SNS Weak Links on Silicon-on Sapphire Substrates

High frequency detector and circuit applications often require device fabrication on medium-to-low-dielectric constant substrates ({var_epsilon}<12). Silicon-on-sapphire (SOS) substrates have acceptably low dielectric constants and provide other important advantages, including the possibility of monolithic integration of silicon and superconducting circuitry. The initial results with YBa{sub 2}Cu{sub 3}O{sub 7{minus}x} (YBCO) edge-geometry superconductor/normal-metal/superconductor (SNS) weak links fabricated on r-plane SOS substrates using cubic zirconia (YSZ) buffer layers revealed problems with grain boundary nucleation in the YBCO counter electrode. These results motivated development of a new multilayer buffer system consisting of an epitaxial YSZ film grown on an SOS substrate, overlayed by a thin YBCO ``seed`` layer, and an epitaxial SrTiO{sub 3} (STO) layer. STO-YBCO bilayers grown over the YBCO seed layer show a remarkable improvement in epitaxial quality and in YBCO electrical properties relative to similar bilayers grown directly on the YSZ buffer. In addition, SNS weak links fabricated on SOS substrates using the multilayer buffer system exhibit dramatically improved electrical characteristics compared to devices produced on YSZ buffer layers. These are the first epitaxial edge geometry SNS weak links produced on SOS substrates.