A post-layout optimization method with automatic device type selection for BiCMOS analog circuits

In this paper, we present a novel post-layout performance optimization method for BiCMOS analog circuits. Its main feature is a new approach for varying the types of non-scalable devices automatically during the design process using a gradient-based optimizer. This greatly extends the design space for BiCMOS circuits in computer-aided circuit optimization and, consequently, the reuse potential for existing circuit topologies and layouts. The method has been demonstrated successfully on the post-layout optimization of a 0.6-µm BiCMOS high-speed operational amplifier.