Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques
2011
a imec, Kapeldreef 75, 3001 Heverlee, Belgium b ESAT-INSYS department, Katholieke Universiteit Leuven, 3000 Leuven, Belgium c also Post-doctoral fellow of the Fund for Scientific Research-Flanders (FWO), 1000 Brussels, Belgium d also IWT-Vlaanderen, 1000 Brussels, Belgium e Sony assignee at imec, 3001 Leuven, Belgium f Currently at IBM g Universita della Calabria, Arcavacata di Rende, Italy h Panasonic assignee at imec, 3001 Leuven, Belgium
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