Analysis and Optimization of Power Supply Rejection for Power Management Unit Design in RFID Sensor applications

This paper presents a methodology for analyzing and optimizing the power supply rejection (PSR) for a Power Management Unit (PMU) in RFID sensor applications. Since RFID design is typically system-on-chip (SoC) that integrates multiple functions on a single chip, multi-frequency supply ripples can be observed. Since the supply ripple is a significant input noise for the sensors, the noise reduction is needed to achieve accurate sensor operations. Firstly, it is necessary to analyze the ripple frequencies from each source. Then, the conventional PMU for the calculation of transfer function is modeled to reveal the system behaviour. Since the crucial factor defining the overall PSR is explained, a system level optimization is given, that requires only a simple modification and can be applied to conventional PMU designs. The simulation results show that the system significantly reduces the input ripple after optimization with an improved PSR from 24 dB to −20 dB. Finally, the theory is applied to a fabricated CMOS design as a case study that achieves a PSR measurement of −26 dB from 400 Hz to 25 MHz.