Graphene for Silicon Microelectronics: Ab Initio Modeling of Graphene Nucleation and Growth

Graphene electronics is expected to complement the conventional Si technologies. Graphene processing should thus be compatible with the mainstream Si technology: CMOS. Ideally, it should be possible to grow graphene directly on a Si wafer, but this does not work. Large area graphene can be grown on Cu or on Ni, its transfer to silicon must then follow, which is problematic. Researchers try therefore to grow graphene on CMOS compatible substrates, such as on Ge/Si(001) wafers. Ab initio modeling, particularly when used in combination with experimental data, can elucidate the mechanisms that govern the process of nucleation and growth of graphene, and thus provide assistance in the design of experiments and production processes. We overview our results in this context, startig from atomic C deposited on (chemically inert) graphene, through the similar cases of Si deposited on graphene and C deposited on hexagonal boron nitride, and the case of carbon on a non-inert insulator (SiO2-like surface of mica), up to C atoms and hydrocarbon molecules building graphene on Ge(001) surfaces.