Reducing Processor Wearout by Exploiting the Timing Slack of Instructions

To combat these runtime degradation issues manufacturers are currently adding guardbands to their designs, to ensure that the chips will be functional for a certain lifetime. However, this overdesign increases development and manufacturing costs, which is crucial for the embedded segment where low costs are a primary target. Hence, new approaches are necessary to take further advantage of scaled technology nodes. Therefore, a lot of research is done at various design levels. To name just a few, special NBTI-resilient circuits, input vector control , power gating , adaptive body biasing, dynamic voltage and frequency scaling (DVFS ), and enhanced instruction and application scheduling techniques are some of the existing aging mitigation methods. The last two techniques try to balance the necessary calculations on the available units (cores) to achieve equal wearout states on all units (cores), which should guarantee a longer lifetime of these parts.