Design methodology for deep submicron CMOS

A design methodology for optimizing deep submicron CMOS devices is proposed, where gate oxide thickness T ox and supply voltage V dd are the main parameters. An operational region where all the constraints are satisfied, is represented in a simple 2D (V dd -T ox ) plane. Parameter optimization for realizing high performance of given circuits can be achieved with excellent prospects. This method was utilized for 0.25µm CMOS design to demonstrate its usefulness. Optimum supply voltage and oxide thickness are expected to be 2V and 6nm, respectively. Sensitivity analysis showed that a surface channel is preferable to a buried channel.