Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults

Abstract In current semiconductor manufacturing processes, embedded memory yield is often improved by including fault tolerance techniques such as built-in self-test and self-repair. The improvement depends on the effectiveness of the memory repair algorithm. One of the existing state-of-art memory repair algorithms with high repair effectiveness is Selected fail count comparison. In this paper, further enhancement of this algorithm is proposed to increase its repair rate by considering special fault types during fault collection such as intersection and orphan faults. For 1 Mb memories with up to 10 spare rows and columns, the experimental results show a significant memory repair rate improvement of up to 5% over the original algorithm at a small area overhead cost averaging at 3,7%. Our results also show that the area overhead can be reduced by using an equal amounts of spare rows and columns, in which case it is negligible.