Counter IP core connected with 16-bit microprocessor application system, and counter counting control realization method thereof

A counter IP core connected with a 16-bit microprocessor application system comprises a data input/output and command word decomposition storage control module, a pulse 200 frequency divider, a counting processing control module, a counter overflow sign control module and an input gated selection control module; the FPGA design counter IP core is in hard connection with a control circuit; the counter IP core comprises 15 16-bit counters, wherein 14 counters can form 7 32-bit counters; one command word sets the work mode of the counter, sets counting filtering reference clock frequency division times, and controls the work state; the counter IP core only uses the 16-bit microprocessor to set functions and states, counting parameter transmission and read counting present value operation of the counters, so program execution time of the 16-bit microprocessor is not used by other programs; each 16/32 bit counter has a counting parameter automatic afresh loading function, thus satisfying counting and counting control system demands of many counters.