SRAM enablement beyond N7: A BTI study

Operating voltage (Vmin) improvement for High density SRAM with scaling is halted due to variability and aging effects which becomes a bottleneck for energy optimized operation. Device level and cell level advancements help the SRAM in lowering Vmin. Assist techniques become beneficial in Vmin lowering but due to BTI their Vmin degrades. BTI sensitivity analysis for these solutions gives insight of BTI resilient HD SRAM design for advanced technology node.