A 250/285 GHz Push-Push Oscillator Using Differential Gate Equalisation in Digital 65-nm CMOS

This study presents a push–push oscillator architecture based on differential gate equalisation to enhance the oscillation frequency while providing relatively high output power with ultra-compact layout form factor. The frequency enhancement is derived as a function of the equivalent RLC model of the oscillator's main constituents. The proposed principle is applied to a terahertz oscillator in the 200–300 GHz range to mitigate the excessive substrate and skin effect losses in standard digital 65-nm complementary metal–oxide–semiconductor technology at such high frequencies. The design concept is validated using two single-stage push–push oscillators. The first oscillator shows −8.1 dBm output power at 250 GHz oscillation frequency and −106.8 dBc/Hz phase noise at 10 MHz offset while consuming 76 mW power from 1.5 V DC supply voltage. The chip area is 200 × 250 μm2. The second oscillator provides −14.8 dBm output power at 285 GHz and −106 dBc/Hz phase noise at 10 MHz offset with 80 mW power consumption from 1.5 V DC supply. The chip area is 200 × 200 μm2.