Review: Parametric Variations in Analog-to-Digital Converters Using Different CMOS Technologies

This paper presents a brief review on analog-to-digital converters based on different CMOS technologies. Various parameters such as signal-to-noise and distortion ratio (SNDR), frequency sample, input frequency, spurious-free dynamic range (SFDR), power and figure of merit (FOM) of analog-to-digital converter are compared on different technology nodes. Different architectures of ADCs and their performance are also compared. It is observed that a 10-bit pipeline ADC operated at 1.8 V supply voltage has low power consumption and serves best among all the ADCs discussed at 0.18 µm technology. A two-way interleaved pipeline ADC with 12-bit 3 GS/s in 40 nm technology is acceptable because of high sampling speed. However, it has high power dissipation as compared to 12-bit successive approximation register ADC. In 28 nm, single-core L P flash ADC has highest sampling speed of 24 GS/s as compared to 12-bit interleaved pipeline ADC and SAR ADC using CDEC.