Viterbi Decoder with Configurable Constraint Length with Bit Error Correction for Satellite Communication

The Viterbi algorithm is an efficient method to decode convolution encoded data using the concept of maximum likelihood estimation. This paper presents the design and FPGA implementation of a Viterbi decoder for satellite communication. The design is coded in Verilog HDL using the Vivado 2017.4 tool and QuestaSim for behavioral and post-layout simulations. The decoder is designed to decode the output of rate half convolution encoder. It successfully decodes data for any constraint length and corrects error up to 4 bits. The implementation is done on the Zynq-7000 development board. The maximum operating frequency achieved is 221.9 MHz with a power consumption of 37.62 mW.