Infusion Doping for Sub‐45 nm CMOS Technology Nodes

The requirements for ultra‐shallow junctions will be difficult to meet for sub‐45 nm CMOS technology nodes with conventional low‐energy ion implantation and fast‐ramp spike annealing. This paper explores the possibility of using infusion doping in conjunction with flash annealing to achieve shallower junctions with lower sheet resistance. No evidence of channeling in (100) and (110) silicon substrates is seen for infusion doping. A detailed investigation is carried out to study the effects of flash anneal parameters. Experimental results indicate that it is possible to achieve Xj in the range ∼12–15 nm with Rs∼1000 Ω/□, which is adequate for the 32 nm technology generation.