Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee

As data center and telecommunication infrastructure bandwidth requirements continue to increase, networking products with 112Gb/s electrical and optical transceivers are beginning to ramp up to support 400GE and beyond. At the same time, the industry is starting to explore paths of scaling high-speed links with data rates greater than 200Gb/s. This session starts with two papers describing the design of ≥200Gb/s PAM-4 transmitters, one using a DSP/DAC approach in 10nm CMOS and another using an analog approach in 28nm CMOS. Another paper pushes the energy efficiency and chip area of a 112Gb/s DSP/DAC-based transmitter. Three papers in this session describe complete 112Gb/s PAM-4 electrical transceivers with emphasis on reconfigurability, power efficiency improvements, link robustness over voltage/temperature variations, and new techniques to support higher channel loss. One paper addresses DAC and ADC design for 400Gb/s coherent optical links. The session concludes with a paper describing a method to implement a large number of DFE taps in an ADC/DSP-based 112Gb/s PAM-4 receiver.