以0.18um CMOS 積體電路技術設計250MHz 4Kb 靜態隨機存取記憶體

Abstract This thesis describes the implementation of a 4Kb static random access memory circuit. In order to correctly perform a read operation at low voltage, the current latched sense amplifier is improved. This thesis is divided into five chapters. The first chapter is the introduction. In the chapter 2, the architecture and the design considerations of SRAM are presented. In chapter 3, we describe the sense amplifiers in detail. The difference of the input resistance makes the delay differ a lot in sensing time. Chapter 4 presents the circuit implementation. A 4Kb SRAM is implemented with a standard 0.18um CMOS process. The access time of SRAM is 2.0557ns. The core circuit of the chip occupies 1.056002 ╳ 1.090342 mm2 and it consumes 15.658mW when working at 250MHz.