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1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
2011
Ôno Kazuo
Yanagawa Yoshimitsu
Kotabe Akira
Sekiguchi Tomonori
Keywords:
Multi-core processor
Computer architecture
Through-silicon via
Parallel computing
High-throughput computing
Gigabit
Architecture
Computer science
Dram
Correction
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