Low power and temperature compatible FinFET based full adder circuit with optimised area

This paper presents an implementation of an improved circuit design of full adder which is 1-bit. The circuit is planned and implemented with use of the FinFETs at 45 nm technology. The proposed adder circuit consists of 9 transistors and called as 9-T adder cell. FinFETs are new emerging transistors which can work n nanometer range and overcome the short channel effects. The simulation of proposed circuit is done in tanner tool version 13.0 using FinFET model files. The simulation is done to compare power, power delay product with supply voltage. The result is also checked for temperature points from −5 to 35 degrees at 0.3V. Finally, the comparison of the circuit performance of the proposed circuits is made with other reported circuits in literatures and more than 99.9% reduction in power consumption is observed.