Selection of operation mode on SOI/MOSFETs for high-resistivity load static memory cell

SOI/MOSFETs are widely known to have some advantages such as reduction of parasitic capacitance, improvement of subthreshold characteristics and increased drive current, compared with bulk-Si/MOSFETs. Moreover, this structure provides the reduction in the substrate-bias effect because the back-gate bias (Si substrate) is applied to the channel region through thick buried oxide. In the present paper, we propose the best choice of operation mode of SOI/MOSFETs in a high-resistivity load SRAM cell to improve the stability in the memory cell and to obtain sufficient static noise margin providing non-destructive reading of cell data at low supply voltage. >