Suppression of the lateral diffusion under the gate of an MOS transistor by argon implantation

A new technique for eliminating the overlap diffusion of the source and drain in MOS devices is reported. This technique involves the implantation of argon in the source and drain regions following the arsenic implant, using the same auto-aligned gate. The results show that, compared to the conventional process, a reduction in the lateral diffusion of arsenic is observed, which results in negligible gate-junction overlap encroachment and a consequent gain in device speed. Furthermore, improvements in source-drain breakdown voltages, punchthrough voltages, and substrate currents are also seen.