Performance improvements in high-density DRAM application using 0.15 /spl mu/m body-contacted SOI technology

A 0.15 /spl mu/m silicon-on-insulator (SOI) CMOS technology, using a body-contacted (BC) SOI structure, is developed. This process technology is fully compatible with bulk CMOS technology except for the isolation process. The key advantage of the BC-SOI MOSFET is that it is free from floating-body effects, since the body-potential increase can be suppressed by the well contact through the remaining thin-silicon film beneath the shallow trench isolation. This technology was applied to 256 Mbit SOI SDRAM, which shows improved refresh characteristics compared with bulk devices.