Parallel and serial data converting circuit based on FPGA

The invention discloses a parallel and serial data converting circuit based on an FPGA. The parallel and serial data converting circuit is composed of a data output selector and pulse generation units capable of generating pluses. The data output selector is a one-out-N selector. Each pulse generation unit is composed of a time-delay unit, an inverter and an AND gate. The time-delay unit is enabled to be precise and controllable using the locating and wiring constraint technology. The parallel and serial data converting circuit provided by the invention can achieve a serial transmission speed of GHz, is achieved using the FPGA design, and has high accuracy, strong versatility and applicability.