A low-power, high-speed 4-bit GaAs ADC and 5-bit DAC

1989 
A 4-b flash analog-to-digital converter (ADC) and 5-b digital-to-analog converter (DAC) have been designed and fabricated in gallium arsenide using a 0.7- mu m MESFET self-aligned gate process. The ADC operates at a 1-GHz sampling rate with a chip power dissipation of only 140 mW, while the DAC consumes only 85 mW of power at a 1-GHz sampling rate. To overcome the material limiting deficiencies of the MESFET in higher-resolution flash ADCS, a subranging technique can be implemented using two ADCs and a DAC. This technique places the resolution limitation primarily on the DAC. >
    • Correction
    • Source
    • Cite
    • Save
    • Machine Reading By IdeaReader
    3
    References
    17
    Citations
    NaN
    KQI
    []