Electronic chips & systems design languages

Contributors. Preface. VHDL Extensions. I: VHDL-AMS - Introduction A. Vachoux. 1. Library Development Using the VHDL-AMS Language E. Christen, K. Bakalar. 2. Behavioral Modeling of Complex Heterogeneous Microsystems P. Schwarz, J. Haase. 3. VHDL-AMS, a Unified Language to Describe Multi-Domain, Mixed-Signals Designs. Mechatronic Applications V. Aubert, S. Garcia-Sabiro. 4. Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique J. Dabrowski, A. Pulka. II: OO-VHDL. 5. SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling P. Ashenden, et al. 6. Digital Circuit Design with Objective VHDL M. Radetzki, W. Nebel. System Level Design. I: HW/SW Co-design. 7. UF: Architecture and Semantics for System-Level Multiformalism Descriptions L.S. Fernandez, et al. 8. Automatic Interface Generation among VHDL Processes in HW/SW Co-Design E. Barros, C. de Araujo. 9. System-Level Specification and Architecture Exploration: An Avionics Codesign Application F. Cloute, et al. 10. Using SDL to Model Reactive Embedded System in a Co-design Environment R. Kumar. 11. A Synchronous Object-Oriented Design Flow for Embedded Applications P.G. Ploger, et al. II: Co-simulation. 12. Heterogeneous System-Level Cosimulation with SDL and Matlab P. Bjureus, A. Jantsch. 13. VHDL-Based HW/SW Cosimulation of Microsystems V. Moser, et al. 14. Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling M.Bauer, et al. III: SLD methodology. 15. A Comparison of Six Languages for System Level Description of Telecom Applications A. Jantsch, et al. 16. High Level Modelling in SDL and VHDL+ F. Cook, et al. 17. ECL: A Specification Environment for System-Level Design E. Sentovich, et al. 18. The MCSE Approach for System-Level Design J.P. Calvez, et al. Synthesis. 19. Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement D. Sciuto, et al. 20. VHDL Dynamic Loop Synthesis M.F. Albenge, D. Houzet. 21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System A.D. Brown, et al. Formal Verification. I: Formal Verification. 22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation A.F. Nicolae, E. Cerny. 23. Formal Verification of VHDL using VHDL-Like ACL2 Models D. Borrione, P. Georgelin. 24. Specification of Embedded Monitors for Property Checking M. Bombana, et al. 25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL O. Drogehorn, et al.