Phase noise reduction of a 2 μm passively mode-locked laser through its hybrid integration with a silicon photonic circuit

Passively mode-locked semiconductor lasers are promising for a wide variety of chip-scale high-speed and high-capacity applications. However, the phase noise/timing jitter of such light sources are normally high, which restricts their applications. A simple and low-cost chip-scale solution to address this issue is highly desired. In this work, a two-section GaSb-based passively mode-locked laser (MLL) emitting in the 2 µm wavelength band with a fundamental repetition frequency of ∼13.35GHz is presented. Dramatic phase noise reduction is achieved through its hybrid integration with a silicon photonic circuit which provides chip-scale optical feedback to the MLL. Under a fixed laser bias condition, more than 50× improvement of radio frequency linewidth to sub-kilohertz level is realized by carefully adjusting the feedback strength (via a p-i-n junction-based variable optical attenuator) and optical length of the feedback loop (via integrated heater on the silicon waveguide). The phase noise reaches −113dBc/Hz at 1 MHz offset with integrated timing jitters of 274 fs (100 kHz to 100 MHz) and 123 fs (4 to 80 MHz). At the same time, the pulse-to-pulse jitter reaches as low as 7.8 fs/cycle. These values are record low for 2 µm passively mode-locked semiconductor lasers. Our results prove the feasibility of MLL noise reduction with the chip-scale hybrid III-V/silicon integration method, bringing low-noise light sources to the silicon platform. Moreover, this work also suggests the potential miniaturization of various other functional setups with the same method.