Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters

In this paper, we proposed a heuristic algorithm for minimizing the critical access time on a 3D data bus based on inserted bus switches and repeaters. Given the topology of a 3D data bus with a number of timing periods, the algorithm first inserts bus switches to isolate those unnecessary local bus capacitive loading by evaluating all the timing periods. Then, it inserts signal repeaters close to their source drivers, which are located on the current critical path, and tunes their sizes to minimize the critical access time. This tuning procedure is repeated until no additional improvement. Some created 3D data buses with various topologies using 45nm technology are tested and experimental results show that our algorithm can dramatically reduce the critical access time of a 3D data bus up to 50.6% on average.