A digital Monolithic Active Pixel Sensor chip in a Quadruple-Well CIS process

A CMOS sensor chip for charged particle detection has been developed and submitted for fabrication in a 0.18 m Quadruple-Well (N&P-Wells, Deep N&P-Wells) CMOS Image Sensor (CIS) process. Improvement of the radiation hardness, the readout speed and the power dissipation of the mainstream CMOS sensors is expected with the exploration of this process. In order to ensure better charge collection and neutron tolerance, wafers with high-resistivity epitaxial layer have been chosen. The chip comprises several sub-chips, and in this paper one of them, a digital CMOS sensor prototype developed in order to validate the key analog blocs (from sensing element to I-bit digital conversion) of a binary MAPS in this process will be presented. The digital sensor prototype comprises four different sub-arrays of 20 μm pitch 64 × 32 pixels, 128 column-level auto-zeroed discriminators, a sequencer and an output digital multiplexer. Laboratory tests results including the charge-to-voltage conversion factor, the charge collection efficiency, the temporal noise and the fixed-pattern noise are presented in details. A 55 Fe source is used for calibration of pixels. Some irradiation results will also be given.