Aging Effects: From Physics to CAD

Advances in technology have steadily paved the way for making embedded systems ubiquitous in our daily life. Compared to previous generations, the current nano-CMOS era introduces reliability challenges at an increased pace. Reliability has become equally important as other conventional design constraints like cost and performance because technology scaling is reaching limits and hence aging phenomena may endanger the functionality of an entire design. Of these phenomena, bias temperature instability (BTI) and hot carrier-induced degradation (HCID) are the most prominent, with the potential to remarkably degrade the key electrical characteristics of pMOS and nMOS transistors. Therefore, there is an ever-increasing need to investigate aging from the physical level, where it does originate all the way up to the system level, where it finally manifests itself. Additionally, reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this chapter, we will first explain the underlying mechanisms of aging at the physical level and how they alter the key parameters of MOSFET transistors at the device level. Then, we will introduce the concept of degradation-aware cell libraries. We will demonstrate how plugging these libraries into the standard design flow will enable designers to not only analyze aging but to also optimize it at the circuit level. Finally, we will discuss that selecting guardbands to protect against aging cannot be independently done from the running workloads at the system level. Otherwise, unnecessary performance losses will be incurred.