Microparticle transfer onto pixel electrodes of 45 μm pitch on HV-CMOS chips. Simulation and experiment

Abstract Spatially selective deposition of electrically charged microparticles onto integrated circuits that generate electrical fields in programmable patterns using electrodes on their surface was previously limited to a pixel pitch of 100 μm. Now, we demonstrate spatially selective deposition onto pixels of 45 μm pitch in experiments on a test chip allowing arbitrary patterns, but being of limited size and of fixed characteristics, complemented by COMSOL simulations. Experiments on a prototype high voltage CMOS chip demonstrate the feasibility of miniaturisation in the first place, imply simulations of interest that cannot be tested experimentally and, conversely, complement the simplified simulation models by reality checks. Using COMSOL for the optimisation of the setup parameters, particles of decreasing average diameter in a number of aerosol and electrical field geometries are simulated with particular attention to minimising contamination (deposition of particles on undesirable locations). Combining these results, the average particle diameter is decreased from 10 μm to less than 3 μm and the deposition voltage is reduced from 100 V to 30 V, when using pixels with a pitch of 45 μm. Optimising these parameters allows for more than quadrupling the spot density compared to the previous chip, on which combinatorial particle deposition with minimal contamination is achieved. Peptide arrays, having been previously shown to be a major application for this method, benefit in particular, as the increase in density from 10,000 pixels/cm 2 to approximately 50,000 pixels/cm 2 promises a significant decrease in cost-per-peptide and amount of test specimens required.