A DLL with Jitter-Reduction Techniques for DRAM Interfaces

A DLL featuring jitter-reduction techniques for a noisy environment is described. Loop behavior is controlled by monitoring the amount of jitter caused by supply noise of a replica delay line. The DLL is implemented in a 0.13mum CMOS process, and at 1 GHz, it has 4.58ps rms jitter and 29ps pp jitter with noisy replica delay line.