Multi-start simulated annealing for partially-reconfigurable FPGA floorplanning

FPGA floorplannig consists in finding a satisfactory placement of the different pre-determined regions of a design, onto the resource matrix that composes the FPGA hardware. Performance is ensured by minimizing the distances between communicating regions, as well as between regions and their I/O ports on the FPGA. To this very challenging problem, additional features can be added, such as taking into account the existence of partially-reconfigurable regions. This paper presents the solution method we proposed in the RAW Floorplanning Desing Contest, organized for the 25th Anniversary of the Reconfigurable ArchitecturesWorkshop (RAW), held in conjunction with the IPDPS’18 conference. The solution method is a multistart simulated annealing procedure, which won the contest.