DESIGN OF AREA EFFICIENT FIR FILTER USING TRUNCATED MULTIPLIER TECHNIQUE FOR DSP APPLICATIONS

Multiplication of two numbers is one of the most area consuming arithmetic operations in high-performance circuits as it generates a product with twice the original bit width. The truncation of product bits to the required precision of truncated multipliers offers significant improvements in area, delay and power. The proposed method reduces the number of full adders and half adders during the tree reduction. Usually the product of two numbers appears as output in the form of LSB and MSB. The LSB part is truncated and compressed using MCMAT technique. In previous related papers, the truncation error is reduced using MCMT technique. In this project, truncation error is not more than 1 ulp (unit of least position). While implementing the proposed method experimentally, there is no need of any error compensation circuits and the final output is precised. Hence the area can be saved and the power is also reduced. To further extend the work, digital FIR filter implementation with MCMAT technique is carried out using Wallace Tree Compressor (WTC).